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| HB56A841BR Series, HB56A441BR Series 8,388,608-word x 40-bit High Density Dynamic RAM Module 4,194,304-word x 40-bit High Density Dynamic RAM Module ADE-203-731A (Z) Rev.1.0 Feb. 20, 1997 Description The HB56A841BR is a 8M x 40 dynamic RAM module, mounted 20 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package. The HB56A441BR is a 4M x 40 dynamic RAM module, mounted 10 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package. An outline of the HB56A841BR, HB56A441BR is 72-pin single in-line package. Therefore, the HB56A841BR, HB56A441BR make high density mounting possible without surface mount technology. The HB56A841BR, HB56A441BR provide common data inputs and outputs. Decoupling capacitors are mounted on the module board. Features * 72-pin single in-line package Outline: 107.95 mm (Length) x 25.40 mm (Height) x 9.14/5.28 mm (Thickness) Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 50/60/70ns (max) * Low power dissipation Active mode: 5.52/4.99/4.46 W (max) (HB56A841BR Series) 5.25/4.73/4.20 W (max) (HB56A441BR Series) Standby mode (TTL): 210 mW (max) (HB56A841BR Series) (TTL): 105 mW (max) (HB56A441BR Series) (CMOS): 105 mW (max) (HB56A841BR Series) (CMOS): 52.5 mW (max) (HB56A441BR Series) * Fast page mode capability * Refresh period 2048 refresh cycles: 32 ms HB56A841BR Series, HB56A441BR Series * 3 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh * TTL compatible Ordering Information Type No. HB56A841BR-5 HB56A841BR-6 HB56A841BR-7 HB56A441BR-5 HB56A441BR-6 HB56A441BR-7 Access time 50 ns 60 ns 70 ns 50 ns 60 ns 70 ns Package 72-pin SIP socket type Contact pad Gold 2 HB56A841BR Series, HB56A441BR Series Pin Arrangement 1Pin 36Pin 37Pin 72Pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Pin name VSS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC PD4 A0 A1 A2 A3 A4 A5 A6 Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin name OE DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A7 DQ16 VCC A8 A9 NC NC DQ17 DQ18 Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Pin name DQ19 DQ20 VSS CAS0 A10 NC CAS1 (NC)* RAS0 RAS1 (NC)* DQ21 WE x 40 (VSS ) DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 2 1 Pin No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Pin name DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 PD0 PD1 PD2 PD3 DQ39 VSS Notes: 1. CAS1: HB56A841BR, NC: HB56A441BR 2. RAS1: HB56A841BR, NC: HB56A441BR 3 HB56A841BR Series, HB56A441BR Series Pin Description Pin name A0 to A10 Function Address inputs: Row address: Column address: Refresh address: DQ0 to DQ39 CAS0, CAS1 RAS0, RAS1 WE OE VCC VSS PD0 to PD4 NC Data-in/Data-out Column address strobe Row address strobe Read/Write enable Output enable Power supply Ground Presence detect pin No connection A0 to A10 A0 to A10 A0 to A10 Presence Detect Pin Arrangement (HB56A841BR) Function Pin No. 67 68 69 70 11 Pin name PD0 PD1 PD2 PD3 PD4 50 ns NC VSS VSS VSS VSS 60 ns NC VSS NC NC VSS 70 ns NC VSS VSS NC VSS Presence Detect Pin Arrangement (HB56A441BR) Function Pin No. 67 68 69 70 11 Pin name PD0 PD1 PD2 PD3 PD4 50 ns VSS NC VSS VSS VSS 60 ns VSS NC NC NC VSS 70 ns VSS NC VSS NC VSS 4 HB56A841BR Series, HB56A441BR Series Block Diagram (HB56A841BR) RAS1 CAS1 RAS0 CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 A0 to A10 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS D0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS D10 CAS RAS D1 CAS RAS D11 CAS RAS D2 CAS RAS D12 CAS RAS D3 CAS RAS D13 CAS RAS D4 CAS RAS D14 CAS RAS D5 CAS RAS D15 CAS RAS D6 CAS RAS D16 CAS RAS D7 CAS RAS D17 CAS RAS D8 CAS RAS D18 CAS RAS D9 CAS RAS D19 D0 - D19 D0 - D19 D0 - D19 D0 - D19 0.22 F x 10 pcs D0 - D19 Note: D0 - D19 : HM5117400 WE OE VCC VSS 5 HB56A841BR Series, HB56A441BR Series Block Diagram (HB56A441BR) RAS0 CAS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 A0 - A10 WE OE VCC VSS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CAS RAS D0 CAS RAS D1 CAS RAS D2 CAS RAS D3 CAS RAS D4 CAS RAS D5 CAS RAS D6 CAS RAS D7 CAS RAS D8 CAS RAS D9 D0 - D9 D0 - D9 D0 - D9 D0 - D9 0.22 F x 10 pcs D0 - D9 Note: D0 - D9 : HM5117400 6 HB56A841BR Series, HB56A441BR Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -1.0 to +7.0 -1.0 to +7.0 50 10 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to 70C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 4.75 2.4 -1.0 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note 7 HB56A841BR Series, HB56A441BR Series DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HB56A841BR) 50 ns Parameter Operating current Standby current 60 ns 70 ns Test conditions t RC = min TTL interface, RAS, CAS = VIH, Dout = High-Z CMOS interface, RAS, CAS VCC - 0.2 V, Dout = High-Z t RC = min RAS = VIH, CAS = VIL, Dout = enable t RC = min t PC = min 0 V Vin 5.5 V 0 V Vout 5.5 V, Dout = disable High Iout = -5 mA Low Iout = 4.2 mA 1, 3 2 1 Notes 1, 2 Symbol Min Max Min Max Min Max Unit I CC1 I CC2 -- -- 1050 -- 40 -- 950 -- 40 -- 850 mA 40 mA -- 20 -- 20 -- 20 mA RAS-only refresh current Standby current CAS-before-RAS refresh current Fast page mode current Input leakage current I CC3 I CC5 I CC6 I CC7 I LI -- -- -- -- 1050 -- 100 -- 1050 -- 950 -- 950 -- 100 -- 950 -- 850 -- 850 mA 100 mA 850 mA 750 mA A A V V -10 10 -10 10 2.4 0 VCC 0.4 -10 10 -10 10 2.4 0 VCC 0.4 -10 10 -10 10 2.4 0 VCC 0.4 Output leakage current I LO Output high voltage Output low voltage VOH VOL Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 8 HB56A841BR Series, HB56A441BR Series DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) (HB56A441BR) 50 ns Parameter Operating current Standby current 60 ns 70 ns Test conditions t RC = min TTL interface, RAS, CAS = VIH, Dout = High-Z CMOS interface, RAS, CAS VCC - 0.2 V, Dout = High-Z t RC = min RAS = VIH, CAS = VIL, Dout = enable t RC = min t PC = min 0 V Vin 5.5 V 0 V Vout 5.5 V, Dout = disable High Iout = -5 mA Low Iout = 4.2 mA 1, 3 2 1 Notes 1, 2 Symbol Min Max Min Max Min Max Unit I CC1 I CC2 -- -- 1000 -- 20 -- 900 -- 20 -- 800 mA 20 mA -- 10 -- 10 -- 10 mA RAS-only refresh current Standby current CAS-before-RAS refresh current Fast page mode current Input leakage current I CC3 I CC5 I CC6 I CC7 I LI -- -- -- -- 1000 -- 50 -- 900 -- 50 -- 800 mA 50 mA 1000 -- 900 -- 900 -- 800 -- 800 mA 700 mA A A V V -10 10 -10 10 2.4 0 VCC 0.4 -10 10 -10 10 2.4 0 VCC 0.4 -10 10 -10 10 2.4 0 VCC 0.4 Output leakage current I LO Output high voltage Output low voltage VOH VOL Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 9 HB56A841BR Series, HB56A441BR Series Capacitance (Ta = 25C, VCC = 5 V 5%) (HB56A841BR) Parameter Input capacitance (Address) Input capacitance (WE, OE) Input capacitance (RAS, CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 140 160 90 25 Unit pF pF pF pF Notes 1 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. Capacitance (Ta = 25C, VCC = 5 V 5%) (HB56A441BR) Parameter Input capacitance (Address) Input capacitance (WE, OE) Input capacitance (RAS, CAS) I/O capacitance (DQ) Symbol CI1 CI2 CI3 CI/O Typ -- -- -- -- Max 90 90 90 20 Unit pF pF pF pF Notes 1 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 10 HB56A841BR Series, HB56A441BR Series AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) *1, *2, *18, *19 Test Conditions * * * * Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) 50 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time OE to Din delay time OE delay time from Din CAS delay time from Din Symbol Min t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH 90 30 7 50 13 0 7 0 7 17 12 13 50 5 13 0 0 3 -- Max -- -- -- 60 ns Min 110 40 10 Max -- -- -- 70 ns Min 130 50 10 Max -- -- -- Unit ns ns ns Notes 10000 60 10000 15 -- -- -- -- 37 25 -- -- -- -- -- -- 50 32 0 10 0 10 20 15 15 60 5 15 0 0 3 -- 10000 70 10000 18 -- -- -- -- 45 30 -- -- -- -- -- -- 50 32 0 10 0 15 20 15 18 70 5 18 0 0 3 -- 10000 ns 10000 ns -- -- -- -- 52 35 -- -- -- -- -- -- 50 32 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 5 6 6 7 3 4 CAS to RAS precharge time t CRP t OED t DZO t DZC Transition time (rise and fall) t T Refresh period (2,048 cycles) t REF 11 HB56A841BR Series, HB56A441BR Series Read Cycle 50 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Symbol Min t RAC t CAC t AA t OEA t RCS -- -- -- -- 0 0 5 25 25 0 3 3 -- -- 13 Max 50 13 25 13 -- -- -- -- -- -- -- -- 13 13 -- 60 ns Min -- -- -- -- 0 0 5 30 30 0 3 3 -- -- 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- 15 15 -- 70 ns Min -- -- -- -- 0 0 5 35 35 0 3 3 -- -- 18 Max 70 18 35 18 -- -- -- -- -- -- -- -- 15 15 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13 13 5 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9, 20 Read command hold time to t RCH CAS Read command hold time to t RRH RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD Write Cycle 50 ns Parameter Write command setup time Write command hold time Write command pulse width Symbol Min t WCS t WCH t WP 0 7 7 13 13 0 7 Max -- -- -- -- -- -- -- 60 ns Min 0 10 10 15 15 0 10 Max -- -- -- -- -- -- -- 70 ns Min 0 15 10 18 18 0 15 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 15 15 Notes 14 Write command to RAS lead t RWL time Write command to CAS lead t CWL time Data-in setup time Data-in hold time t DS t DH 12 HB56A841BR Series, HB56A441BR Series Read-Modify-Write Cycle 50 ns Parameter Symbol Min 131 73 36 48 13 Max -- -- -- -- -- 60 ns Min 155 85 40 55 15 Max -- -- -- -- -- 70 ns Min 181 98 46 63 18 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes Read-modify-write cycle time t RWC RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE t RWD t CWD t AWD t OEH Refresh Cycle 50 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) Symbol Min t CSR t CHR t WRP t WRH 5 7 0 7 5 Max -- -- -- -- -- 60 ns Min 5 10 0 10 5 Max -- -- -- -- -- 70 ns Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns Notes RAS precharge to CAS hold t RPC time Fast Page Mode Cycle 50 ns Parameter Fast page mode cycle time Symbol Min t PC 35 -- -- 30 Max -- 60 ns Min 40 Max -- 70 ns Min 45 Max -- Unit ns 16 9, 17 Notes Fast page mode RAS pulse t RASP width Access time from CAS precharge RAS hold time from CAS precharge t CPA t CPRH 100000 -- 30 -- -- 35 100000 -- 35 -- -- 40 100000 ns 40 -- ns ns 13 HB56A841BR Series, HB56A441BR Series Fast Page Mode Read-Modify-Write Cycle 50 ns Parameter Fast page mode readmodify-write cycle time WE delay time from CAS precharge Symbol Min t PRWC t CPW 76 53 Max -- -- 60 ns Min 85 60 Max -- -- 70 ns Min 96 68 Max -- -- Unit ns ns 14 Notes 14 HB56A841BR Series, HB56A441BR Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) is define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t CPW and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min) or tCWD tCWD (min), tAWD tAWD (min) and tCPW t CPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. These parameters are referred to CAS leading edge in early write cycle and to WE leading edge in delayed write or read-modify-write cycles. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among t AA , t CAC or tCPA. 18. In delayed write or read-modify-write cycle, OE must disable output buffer prior to applying data to the device. After RAS is reset, if tOEH tCWL, the DQ pin will remain open circuit (high impedance); if t OEH tCWL, invalid data will be out at each DQ. 19. All the V CC and VSS pins shall be supplied with the same voltages. 20. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally causes large V CC / VSS line noise, which causes to degrade V IH min / V IL max level. 21. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 15 HB56A841BR Series, HB56A441BR Series Timing Waveforms*21 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t ASC t RAL t CAL t CAH t RAH Address Row Column t RRH t RCS t RCH WE t DZC t CDD Din High-Z t DZO t OEA t OED OE t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO 16 HB56A841BR Series, HB56A441BR Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) 17 HB56A841BR Series, HB56A441BR Series Delayed Write Cycle*18 t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Address Row Column t CWL t RCS t RWL t WP WE t DZC t DS t DH Din High-Z Din t OEH t OED t DZO t OEZ t CLZ Dout High-Z Invalid Dout 18 OE HB56A841BR Series, HB56A441BR Series Read-Modify-Write Cycle*18 t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC t CAH Address Row t RCS Column t CWD t AWD t RWD t CWL t RWL t WP WE t DZC t DS Din High-Z Din t DH t DZO t OED t OEA t OEH OE t CAC t AA t RAC t OEZ t OHO High-Z Dout t CLZ Dout 19 HB56A841BR Series, HB56A441BR Series RAS-Only Refresh Cycle t RC t RAS RAS tT t CRP CAS t RPC t CRP t RP t ASR t RAH Address Row t OFF Dout High-Z 20 HB56A841BR Series, HB56A441BR Series CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC CAS t CSR tT t CHR t RPC t CRP t RAS t RP , t CP t WRP t WRH t CP WE Address t OFF Dout High-Z 21 HB56A841BR Series, HB56A441BR Series Hidden Refresh Cycle t RC t RAS t RC t RAS t RC t RP t RAS t RP t RP RAS tT t RSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t RAL t CAH t CHR t CRP Column t WRP t RCS t RRH t WRH WE t DZC High-Z Din t DZO t OEA OE t CAC t AA t RAC t CLZ Dout Dout t WRP t WRH t CDD t OED t OEZ t OHO t OFF t OH 22 HB56A841BR Series, HB56A441BR Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RCS t RCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED t RCH t RCH t RCS t RRH t RCH t DZC t CDD High-Z t DZO t OED , OE t RAC t AA t OH t CPA t AA t OH t CPA t AA t OH t OEA t OHO t OEA t OHO t OFF t OEZ t OHO t OEA t CAC t CLZ t OFF t CAC t OEZ t CLZ t CAC t CLZ t OFF t OEZ Dout Dout 1 Dout 2 Dout N 23 HB56A841BR Series, HB56A441BR Series Fast Page Mode Early Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS t PC t CP t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address ROW Column 1 Column 2 Column N t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) 24 HB56A841BR Series, HB56A441BR Series Fast Page Mode Delayed Write Cycle*18 t RASP t RP RAS tT t CSH t RCD CAS t RAD t ASR t RAH Address Row t ASC t CAH Column 1 t CWL t RCS WE t WP t DZC t DS t DH Din t DZO t OED Din 1 t DZO t OED t WP t DZC t DS t DH Din 2 t DZO t OED t WP t DZC t DS t DH Din N t RCS t ASC t CAH Column 2 t CWL t RCS t ASC t CAH Column N t CWL t RWL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP * t OEH t OEH t OEH OE t CLZ t CLZ t CLZ t OEZ t OEZ t OEZ Dout High-Z Invalid Dout Invalid Dout Invalid Dout 25 HB56A841BR Series, HB56A441BR Series Fast Page Mode Read-Modify-Write Cycle*18 t RASP t RP RAS tT t CP t RCD CAS t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t PRWC t CP t CAS t CAS t RSH t CAS t CRP t ASC t CAH Column 2 t CWL t RCS t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL Address t WP t DZC t DS t DH Din 2 t OED t OEH t DZO t OED t WP t DZC t DS t DH Din N Din 1 t DZO t OEH t OEH * OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ High-Z Dout Dout 1 Dout 2 Dout N 26 HB56A841BR Series, HB56A441BR Series Physical Outline HB56A841BR Series Unit: mm inch Front side 107.95 4.25 101.19 3.98 2-O 3.175 0.125 R1.57 R0.062 6.35 0.25 2.03 0.08 6.35 0.25 9.14 max 0.36 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 72 A 1.27 typ. 0.05 44.45 1.75 R1.57 R0.062 6.35 0.25 44.45 1.75 ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,,,, ,, 10.16 0.40 25.40 1.00 2.54 min. 0.10 + 0.10 1.27 - 0.08 + 0.004 0.05 - 0.003 Back side 1 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Detail A 2.54 min 0.10 1.04 0.03 0.041 0.001 0.25 max 0.01 3.17 min 0.125 5.72 min 0.225 72 27 HB56A841BR Series, HB56A441BR Series HB56A441BR Series Unit: mm inch Front side 107.95 4.25 101.19 3.98 2-O 3.175 0.125 R1.57 R0.062 6.35 0.25 2.03 0.08 6.35 0.25 5.28 max 0.208 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 72 A 1.27 typ. 0.05 44.45 1.75 R1.57 R0.062 72 1 6.35 0.25 44.45 1.75 2.54 min. 0.10 10.16 0.40 25.40 1.00 ,, ,, ,, ,, ,, ,, ,, + 0.10 1.27 - 0.08 + 0.004 0.05 - 0.003 Back side Detail A 2.54 min 0.10 1.04 0.03 0.041 0.001 0.25 max 0.01 28 3.17 min 0.125 HB56A841BR Series, HB56A441BR Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 29 HB56A841BR Series, HB56A441BR Series Revision Record Rev. 1.0 Date Feb. 20, 1997 Contents of Modification Initial issue Drawn by Approved by 30 |
Price & Availability of 56A841
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